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M65KG256AB Datasheet(PDF) 31 Page - STMicroelectronics

Part # M65KG256AB
Description  256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM
PDF  51 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M65KG256AB Datasheet(HTML) 31 Page - STMicroelectronics

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M65KG256AB
7 DC and AC parameters
31/51
Figure 6.
Consecutive Bank(Row) Activate Command
1.
The above figure shows consecutive Bank(Row) Activate commands issued to different banks. A tRRD delay must be
respected between two consecutive Bank(Row) Activate commands (ACT) to different banks. If the destination row is
already active, the bank must be precharged to close the row; the ACT command can then be issued tRP after the PRE
command.
2.
Consecutive ACT commands to the same bank must be issued at a tRC interval and separated by a Precharge command
(PRE).
Figure 7.
Read followed by Read in Same Bank and Row
1.
The consecutive READ command must be issued after a minimum delay of tCK to interrupt the previous Read operation.
2.
To issue the consecutive READ to a different row, precharge the bank (PRE) to interrupt the previous Read operation. tRP
after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD after the ACT
command.
BA0-BA1
Row 0
Address
Row 1
ACT
ACT
NOP
Command
K
K
ai11210
tRRD
PRE
tRC
Bank A
Active
NOP
ACT
NOP
Row 0
Bank D
Active
Precharge
Bank A
Bank A
Active
ACT
READ
READ
Command
K
K
DOA0 DOA1
UDQS, LDQS
DQ0-DQ15
DOB0 DOB1
ai11205
Note: 1. Burst Length = 4
2. CAS Latency = 3
3. Bank = Bank A
NOP
Row
Column B
Address
BA0-BA1
NOP
Column A
DOB2
Bank A
Active
Read from
Column A
Data Read from
Column A
Data Read from
Column B
DOB3
Read from
Column B
tRCD



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