M65KG256AB datasheet(43/51 Pages) STMICROELECTRONICS

Part #	M65KG256AB

Description	256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM

PDF	51 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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43 / 51 page

M65KG256AB

7 DC and AC parameters

43/51

Figure 22. Write followed by Read in the same Bank and Row (Write Interrupted)

UDQM/LDQM must be input 1 clock cycle prior to the READ command to prevent invalid data from being written. If the

READ command is input on the next cycle after the WRIT command, UDQM/LDQM are not necessary.

If the Read operation is issued to a different row in the same bank, or to an idle row in a different bank, a Precharge

command (PRE) must be issued before the READ command. In this case, the Read operation does not interrupt the Write

operation.

If the Read operation is issued to a different bank, and to an active row, the sequence is identical to the one described in

Note 1

Command

DI1

UDQS,

LDQS

DQ0-DQ15

WRIT

DI0

ai10839

READ

NOP

Note: 1. Burst Length = 4

2. CAS Latency = 3 (CL)

UDQM,

LDQM

DO0 DO1 DO2

Data Input Masked

Data Output

DI2

DO3

M65KG256AB Datasheet(PDF) 43 Page - STMicroelectronics