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M65KG256AB Datasheet(PDF) 30 Page - STMicroelectronics |
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M65KG256AB Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 51 page  7 DC and AC parameters M65KG256AB 30/51 Table 16. AC Characteristics Measured in Clock Period Symbol Alt Parameter M65KG256AB Unit Min Max tBSTW (1) Burst Read Terminate Command to Write Command Delay Time 3 tCK tBSTZ (1) Burst Read Terminate Command to Data Output Hi-Z 3 tCK tCHW tCH Clock High Pulse Width 0.45 0.55 tCK tCLW tCL Clock Low Pulse Width 0.45 0.55 tCK tDAL Autoprecharge write recovery and precharge time 2tCK + 22.5 ns tDMD UDQM/LDQM to Data Input Latency 0 tCK tDQSS Write Command to First UDQS/LDQS Latching Transition 0.75 1.25 tCK tDSS (2) UDQS/LDQS Falling Edge to K Setup Time 0.2 tCK tDSH (2) UDQS/LDQS Falling Edge Hold Time from K 0.2 tCK tDQSH UDQS/LDQS High Pulse Width 0.35 tCK tDQSL UDQS/LDQS Low Pulse Width 0.35 tCK tDPE tPDEN Power-Down Entry Time 1 tCK tDPX tPDEX Power-Down Exit Time 1 tCK tMRD Mode Register Set Cycle Time 2 tCK tPROZ (1) 1. CAS Latency equals 3 clock cycles. tHZP Precharge Command to Data Output High-Z 3 tCK tRPRE Read Preamble Time 0.9 1.1 tCK tRPST Read Postamble Time 0.4 0.6 tCK tRFC RAS Cycle Time (Auto Refresh to Bank Active in Auto Refresh mode) 15 tCK tRPD Delay Time from Read to Precharge Command (same Bank) BL/2(3) tCK tRWD Delay Time from Read to Write Command (all data output) 3+BL/2(3) tCK tWTR Write to Read command Delay 1 tCK tWPRE Write Preamble 0.25 tCK tWPST (2) 2. The transition for Low-Z to High-Z occur when the device outputs become floating. No specific reference voltage is given in this document. Data Strobe Low Pulse Width (Write Postamble) 0.4 0.6 tCK tWRD Delay Time from Write to Read Command (all data input) 2+BL/2(3) tCK tWPD Delay Time from Write to Precharge Command (same Bank) 3+BL/2(3) 3. BL stands for Burst Length. tCK tWCD Write Command to Data Input Latency 1 tCK tWR Write Recovery Time 2 tCK |
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