M65KG256AB datasheet(29/51 Pages) STMICROELECTRONICS

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M65KG256AB

7 DC and AC parameters

29/51

Table 15.

AC Characteristics

Symbol

Alt

Parameter

M65KG256AB(1)

The above timings are measured according to the test conditions shown in Table 10: Operating and AC Measurement

Conditions.

Unit

Min

Max

tAC

(2)

These timings define the signal transition delays from K or K cross point, that is when K or K signal crosses VREF.

Data Output Access Time from K and K

1.5

6.0

tAS

(3)

tIS

Address and Control Input Setup Time

1.4

tAH

(3)

tIH

Address Control Input Hold Time

1.4

tCK

Clock Cycle Time

7.5

tDQSCK

(2)

UDQS/LDQS Access Time from K and K

1.5

6.0

tDQSHZ

(5)

UDQS/LDQS High-Z Time from K and K

1.5

6.0

tDQSLZ

(6)

UDQS/LDQS Low-Z Time from K and K

1.5

6.0

tDQSQ

(3)

3. The timing reference level is VREF.

UDQS/LDQS to Data Output Skew

0.65

tDV

(4)

4. tDV defines the delay between two successive transitions of the data output signals, that is when DQ0-DQ15

cross VREF.

Data Output Valid to Data Output Transition Time

tDS

(3)

Data Input and UDQM/LDQM Setup Time

0.9

tDH

(3)

Data Input and UDQM/LDQM Hold Time

0.9

tOHZ

(5)

tOHZ and tDQSHZ define the transition time from Low-Z to High-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read

operation, respectively. They specify when data outputs stop being driven.

tHZ

Data Output High-Z Time from K and K

1.5

6.0

tOLZ

(6)

tOLZ and tDQSLZ define the transition time from High-Z to Low-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read

operation. They specify when data outputs begin to be driven.

tLZ

Data Output Low-Z Time from K and K

1.5

6.0

tRAS

RAS Active Time (Bank (Row) Activate to Bank Precharge)

120000

tRC

RAS Cycle Time (Bank (Row) Activate to Bank Activate in Auto

Refresh mode)

tRCD

Delay Time, from RAS Active to CAS Active

tRRD

Delay Time, from RAS Active to RAS Bank Active

tRP

RAS Precharge Time

22.5

tREF

Average Periodic Refresh Time

7.8

µs

tSRE

tSREX

Self Refresh Exit Time

tWPRES

Write Preamble Setup Time

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