M65KG256AB datasheet(32/51 Pages) STMICROELECTRONICS

Part #	M65KG256AB

Description	256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM

PDF	51 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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32 / 51 page

7 DC and AC parameters

M65KG256AB

32/51

Figure 8.

Read followed by Read in a Different Bank

If the consecutive Read operation targets an active row, the second READ command must be issued after a minimum

delay of tCK to interrupt the previous Read operation.

If the consecutive Read operation targets an idle row, precharge the bank (PRE) without interrupting the previous Read

operation. tRP after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD

after the ACT command.

Figure 9.

Read with Auto Precharge

ACT

NOP

Command

DOA0 DOA1

UDQS/

LDQS

DQ0-DQ15

DOB0 DOB1

ai11206

Note: 1. Burst Length = 4

2. CAS Latency = 3

Row 0

Address

BA0-BA1

NOP

Row 1

DOB2

Bank A

Active

Read from

Bank A

Data Read from

Bank A

Data Read from

Bank D

DOB3

READ

NOP

Column A Column B

Bank D

Active

Read from

Bank D

Read from

Column A

Read from

Column B

tRCD

ACT

READA

NOP

Command

DO0 DO1

UDQS, LDQS

DQ0-DQ15

DO2 DO3

ai10586

Note: Burst Length = 2

tRCD

ACT

tRPD

tRAS

tRP (min)

tAC

tDQSCK

Start of

Internal

Auto Precharge cycle

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