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PIC16F18344-I/SS Datasheet(PDF) 33 Page - Microchip Technology |
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PIC16F18344-I/SS Datasheet(HTML) 33 Page - Microchip Technology |
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33 / 489 page  Bank 3 CPU CORE REGISTERS; see Table 4-2 for specifics 18Ch ANSELA ― ― ANSA5 ANSA4 ― ANSA2 ANSA1 ANSA0 --xx -xxx --uu -uuu 18Dh ANSELB X ― Unimplemented — — ― ANSB7 ANSB6 ANSB5 ANSB4 ― ― ― ― xxxx ---- uuuu ---- 18Eh ANSELC ― ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 --xx xxxx --uu uuuu ― X ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 xxxx xxxx uuuu uuuu 18Fh ― ― Unimplemented — — 190h ― ― Unimplemented — — 191h ― ― Unimplemented — — 192h ― ― Unimplemented — — 193h ― ― Unimplemented — — 194h ― ― Unimplemented — — 195h ― ― Unimplemented — — 196h ― ― Unimplemented — — 197h VREGCON(1) ― ― ― ― ― ― VREGPM Reserved ---- --01 ---- --01 198h ― ― Unimplemented — — 199h RC1REG RC1REG<7:0> 0000 0000 0000 0000 19Ah TX1REG TX1REG<7:0> 0000 0000 0000 0000 19Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000 19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TMRT TX9D 0000 0010 0000 0010 19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note 1: Only on PIC16F18324/18344. 2: Register accessible from both User and ICD Debugger. |
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