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PIC16F18344-I/SS Datasheet(PDF) 73 Page - Microchip Technology |
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PIC16F18344-I/SS Datasheet(HTML) 73 Page - Microchip Technology |
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73 / 489 page ![]() 2015-2017 Microchip Technology Inc. DS40001800C-page 73 PIC16(L)F18324/18344 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON0 register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 00 1 1 1 0 x 1 1 Power-on Reset 00 1 1 1 0 x 0 x Illegal, TO is set on POR 00 1 1 1 0 x x 0 Illegal, PD is set on POR 00 u 1 1 u 0 1 1 Brown-out Reset uu 0 u u u u 0 u WDT Reset uu u u u u u 0 0 WDT Wake-up from Sleep uu u u u u u 1 0 Interrupt Wake-up from Sleep uu u 0 u u u u u MCLR Reset during Normal Operation uu u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1u u u u u u u u Stack Overflow Reset (STVREN = 1) u1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS Condition Program Counter STATUS Register PCON0 Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during Normal Operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu Brown-out Reset 0000h ---1 1000 00-1 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-u uuuu RESET Instruction Executed 0000h ---u uuuu uu-u u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. |
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