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PIC16F18344-I/SS Datasheet(PDF) 52 Page - Microchip Technology |
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PIC16F18344-I/SS Datasheet(HTML) 52 Page - Microchip Technology |
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52 / 489 page  Bank 30 CPU CORE REGISTERS; see Table 4-2 for specifics F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu F24h CLC3CON LC3EN ― LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-00 0000 0-00 0000 F25h CLC3POL LC3POL ― ― ― LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu F26h CLC3SEL0 ― ― LC3D1S<5:0> --xx xxxx --uu uuuu F27h CLC3SEL1 ― ― LC3D2S<5:0> --xx xxxx --uu uuuu F28h CLC3SEL2 ― ― LC3D3S<5:0> --xx xxxx --uu uuuu F29h CLC3SEL3 ― ― LC3D4S<5:0> --xx xxxx --uu uuuu F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu F2Eh CLC4CON LC4EN ― LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-00 0000 0-00 0000 F2Fh CLC4POL LC4POL ― ― ― LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu F30h CLC4SEL0 ― ― LC4D1S<5:0> --xx xxxx --uu uuuu F31h CLC4SEL1 ― ― LC4D2S<5:0> --xx xxxx --uu uuuu F32h CLC4SEL2 ― ― LC4D3S<5:0> --xx xxxx --uu uuuu F33h CLC4SEL3 ― ― LC4D4S<5:0> --xx xxxx --uu uuuu F34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu F35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu F36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu F37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note 1: Only on PIC16F18324/18344. 2: Register accessible from both User and ICD Debugger. |
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