PIC16F18344-ISLASHSS datasheet(83/489 Pages) MICROCHIP

83 / 489 page

 2015-2017 Microchip Technology Inc.

DS40001800C-page 83

PIC16(L)F18324/18344

7.3

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the New Oscillator Source (NOSC) and New Divider

Selection Request (NDIV) bits of the OSCCON1

• External Oscillator (EXTOSC)

• High-Frequency Internal Oscillator (HFINTOSC)

• Low-Frequency Internal Oscillator (LFINTOSC)

• Secondary Oscillator (SOSC)

• EXTOSC with 4x PLL

• HFINTOSC with 2x PLL

7.3.1

NEW OSCILLATOR SOURCE

(NOSC) AND NEW DIVIDER

SELECTION REQUEST (NDIV) BITS

The New Oscillator Source (NOSC) and New Divider

Selection Request (NDIV) bits of the OSCCON1

that are used for the CPU and peripherals.

When the new values of NOSC<2:0> and NDIV<3:0>

are written to OSCCON1, the current oscillator

selection will continue to operate as the system clock

while waiting for the new source to indicate that it is

stable and ready. In some cases, the newly requested

source may already be in use, and is ready

immediately. In the case of a divider-only change, the

new and old sources are the same and are ready

immediately. The device may enter Sleep while waiting

for the switch as described in Section 7.3.3 “Clock

Switch and Sleep”

When the new oscillator is ready, the New Oscillator is

Ready (NOSCR) bit of OSCCON3 and the Clock

Switch Interrupt Flag (CSWIF) bit of PIR3 become set

(CSWIF = 1). If Clock Switch Interrupts are enabled

(CSWIE = 1), an interrupt will be generated at that time.

The Oscillator Ready (ORDY) bit of OSCCON3 can

also be polled to determine when the oscillator is ready

in lieu of an interrupt.

If the Clock Switch Hold (CSWHOLD) bit of OSCCON3

is clear, the oscillator switch will occur when the New

Oscillator Ready bit (NOSCR) is set and the interrupt (if

enabled) will be serviced at the new oscillator setting.

If CSWHOLD is set, the oscillator switch is suspended,

while execution continues using the current (old) clock

source. When the NOSCR bit is set, software should:

• set CSWHOLD = 0 so the switch can complete, or

• copy COSC into NOSC<2:0> to abandon the

switch.

If DOZE is in effect, the switch occurs on the next clock

cycle, whether or not the CPU is operating during that

cycle.

Changing the clock post-divider without changing the

clock source (i.e., changing FOSC from 1 MHz to 2

MHz) is handled in the same manner as a clock source

change, as described previously. The clock source will

already be active, so the switch is relatively quick.

CSWHOLD must be clear (CSWHOLD = 0) for the

switch to complete.

The current COSC and CDIV are indicated in the

OSCCON2 register up to the moment when the switch

actually occurs, at which time OSCCON2 is updated

and ORDY is set. NOSCR is cleared by hardware to

indicate that the switch is complete.

7.3.2

PLL INPUT SWITCH

Switching between the PLL and any non-PLL source is

managed as described above. The input to the PLL is

established when NOSC<2:0> selects the PLL, and

maintained by the COSC setting.

When NOSC<2:0> and COSC select the PLL with

different input sources, the system continues to run

using the COSC setting, and the new source is enabled

per NOSC<2:0>. When the new oscillator is ready (and

CSWHOLD = 0), system operation is suspended while

the PLL input is switched and the PLL acquires lock.

7.3.3

CLOCK SWITCH AND SLEEP

If OSCCON1 is written with a new value and the device

is put to Sleep before the switch completes, the switch

will not take place and the device will enter Sleep

mode.

When the device wakes from Sleep and the

CSWHOLD bit is clear, the device will wake with the

‘new’ clock active, and the Clock Switch Interrupt Flag

bit (CSWIF) will be set.

When the device wakes from Sleep and the

CSWHOLD bit is set, the device will wake with the ‘old’

clock active and the new clock will be requested again.

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