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PIC16F18344-I/SS Datasheet(PDF) 82 Page - Microchip Technology

Part # PIC16F18344-I/SS
Description  Full-Featured, Low Pin Count Microcontrollers with XLP
PDF  489 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F18344-I/SS Datasheet(HTML) 82 Page - Microchip Technology

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PIC16(L)F18324/18344
DS40001800C-page 82
 2015-2017 Microchip Technology Inc.
7.2.2.3
Internal Oscillator Frequency
Adjustment
The HFINTOSC and LFINTOSC internal oscillators are
both factory-calibrated. The HFINTOSC oscillator can
be adjusted in software by writing to the OSCTUNE
register (Register 7-3). OSCTUNE does not affect the
LFINTOSC frequency.
The default value of the OSCTUNE register is 00h. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the
HFINTOSC oscillator frequency will begin shifting to the
new frequency. Code execution continues during this
shift. There is no indication that the shift has occurred.
7.2.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a factory calibrated 31 kHz internal clock source.
The LFINTOSC is the clock source for the Power-up
Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM). The LFINTOSC can also be
used as the system clock, or as a clock or input source
to certain peripherals.
The LFINTOSC is selected as the clock source through
one of the following methods:
• Programming the RSTOSC<2:0> bits of
Configuration Word 1 to enable LFINTOSC.
• Write to the NOSC<2:0> bits of the OSCCON1
register.
7.2.2.5
Oscillator Status and Manual Enable
The ‘ready’ status of each oscillator is displayed in the
OSCSTAT1 register (Register 7-4). The oscillators can
also be manually enabled through the OSCEN register
(Register 7-5). Manual enables make it possible to
verify the operation of the EXTOSC or SOSC crystal
oscillators. This can be achieved by enabling the
selected oscillator, then watching the corresponding
‘ready’ state of the oscillator in the OSCSTAT1 register.



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