WM8956CGEFLSLASHV datasheet(43/80 Pages) WOLFSON

43 / 80 page

Production Data

WM8956

PD, November 2011, Rev 4.1

Figure 22 Master Mode

Figure 23 Slave Mode

BCLK DIVIDE

The BCLK frequency is controlled by BCLKDIV[3:0]. See Clocking and Sample Rates section for

more information.

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 24 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 25 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

BCLK

DACDAT

DACLRC

WM8956

DAC

DSP

ENCODER/

DECODER

BCLK

DACDAT

DACLRC

WM8956

DAC

DSP

ENCODER/

DECODER

WM8956CGEFL/V Datasheet(PDF) 43 Page - Wolfson Microelectronics plc