WM8956CGEFLSLASHV datasheet(62/80 Pages) WOLFSON

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WM8956

Production Data

PD, November 2011, Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

DACMR

DAC Soft Mute Ramp Rate

0 = Fast ramp (fs/2, providing maximum delay of

10.7ms at fs=48k)

1 = Slow ramp (fs/32, providing maximum delay

of 171ms at fs=48k)

Output Signal

Path

DACSLOPE

Selects DAC filter characteristics

0 = Normal mode

1 = Sloping stopband

Output Signal

Path

Reserved

R7 (07h)

Audio

Interface

Reserved

BCLKINV

BCLK invert bit (for master and slave modes)

0 = BCLK not inverted

1 = BCLK inverted

Audio Interface

Control

Master / Slave Mode Control

0 = Enable slave mode

1 = Enable master mode

Audio Interface

Control

DLRSWAP

Left/Right DAC Channel Swap

0 = Output left and right data as normal

1 = Swap left and right DAC data in audio

interface

Audio Interface

Control

LRP

Right, left and I

2S modes – LRCLK polarity

0 = normal LRCLK polarity

1 = invert LRCLK polarity

Audio Interface

Control

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising edge

after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising edge

after LRC rising edge (mode B)

3:2

WL[1:0]

Audio Data Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see Note)

Audio Interface

Control

1:0

FORMAT[1:0]

00 = Right justified

01 = Left justified

10 = I

2S Format

11 = DSP Mode

Audio Interface

Control

R8 (08h)

Clocking

(2)

8:6

DCLKDIV[2:0]

111

Class D switching clock divider.

000 = Reserved

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

Class D Speaker

Outputs;

Clocking and

Sample Rates

5:4

Reserved

WM8956CGEFL/V Datasheet(PDF) 62 Page - Wolfson Microelectronics plc

WM8956CGEFL/V Datasheet(HTML) 62 Page - Wolfson Microelectronics plc

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