WM8956CGEFLSLASHV datasheet(46/80 Pages) WOLFSON

46 / 80 page

WM8956

Production Data

PD, November 2011, Rev 4.1

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised in

Table 27. MS selects audio interface operation in master or slave mode. In Master mode BCLK and

DACLRC are outputs. The frequency of DACLRC is set by the DACDIV bits and the frequency of

BCLK is set by the BCLKDIV bits (See "Clocking and Sample Rates"). In Slave mode BCLK and

DACLRC are inputs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Digital Audio

Interface

Format

BCLKINV

BCLK invert bit (for master and slave

modes)

0 = BCLK not inverted

1 = BCLK inverted

Master / Slave Mode Control

0 = Enable slave mode

1 = Enable master mode

DLRSWAP

Left/Right DAC Channel Swap

0 = Output left and right data as normal

1 = Swap left and right DAC data in

audio interface

LRP

Right, left and I

2S modes – LRCLK

polarity

0 = normal LRCLK polarity

1 = invert LRCLK polarity

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

3:2

WL[1:0]

Audio Data Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see Note)

1:0

FORMAT[1:0]

Audio Data Format Select

00 = Right justified

01 = Left justified

10 = I

2S Format

11 = DSP Mode

Table 27 Audio Data Format Control

Note:

Right Justified mode does not support 32-bit data.

AUDIO INTERFACE OUTPUT TRISTATE

mode (MS=0) DACLRC and BCLK are by default configured as inputs (see Table 28).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24 (18h)

Additional

Control (2)

TRIS

Switches DACLRC and BCLK to inputs.

0 = DACLRC and BCLK are inputs (slave mode)

or outputs (master mode)

1 = DACLRC and BCLK are inputs

Table 28 Tri-stating the Audio Interface

WM8956CGEFL/V Datasheet(PDF) 46 Page - Wolfson Microelectronics plc

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