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WM8956CGEFL/V Datasheet(PDF) 52 Page - Wolfson Microelectronics plc |
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WM8956CGEFL/V Datasheet(HTML) 52 Page - Wolfson Microelectronics plc |
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52 / 80 page ![]() WM8956 Production Data w PD, November 2011, Rev 4.1 52 SYSCLK (=MCLK OR PLL OUTPUT) (MHz) BCLKDIV[3:0] BCLK RATE (MASTER MODE) (MHz) MAXIMUM WORD LENGTH (AT MAXIMUM DAC SAMPLE RATE) 12.288 0000 (=1) 12.288 32 0001 (=1.5) 8.192 32 0010 (=2) 6.144 32 0011 (=3) 4.096 32 0100 (=4) 3.072 32 0101 (=5.5) 2.2341818 20 0110 (=6) 2.048 20 0111 (=8) 1.536 16 1000 (=11) 1.117091 8 1001 (=12) 1.024 8 1010 (=16) 0.768 8 1011 (=22) 0.558545 N/A 1100 (=24) 0.512 N/A 1101 (=32) 0.384 N/A 1110 (=32) 0.384 N/A 1111 (=32) 0.384 N/A 11.2896 0000 (=1) 11.2896 32 0001 (=1.5) 7.5264 32 0010 (=2) 5.6448 32 0011 (=3) 3.7632 32 0100 (=4) 2.8224 32 0101 (=5.5) 2.052655 20 0110 (=6) 1.8816 20 0111 (=8) 1.4112 16 1000 (=11) 1.026327 8 1001 (=12) 0.9408 8 1010 (=16) 0.7056 8 1011 (=22) 0.513164 N/A 1100 (=24) 0.4704 N/A 1101 (=32) 0.3528 N/A 1110 (=32) 0.3528 N/A 1111 (=32) 0.3528 N/A Table 33 BCLK Divider in Master Mode |
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