WM8956CGEFLSLASHV datasheet(57/80 Pages) WOLFSON

57 / 80 page

Production Data

WM8956

PD, November 2011, Rev 4.1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Power

Management

(1)

8:7

VMIDSEL

Vmid Divider Enable and Select

00 = Vmid disabled (for OFF mode)

01 = 2 x 50k

 divider enabled (for playback /

record)

10 = 2 x 250k

 divider enabled (for low-

power standby)

11 = 2 x 5k

 divider enabled (for fast start-

up)

VREF

VREF (necessary for all other functions)

0 = Power down

1 = Power up

AINL

Analogue Input PGA and Boost Left

0 = Power down

1 = Power up

(Note: LMIC must also be set to enable the

PGA)

AINR

Analogue Input PGA and Boost Right

0 = Power down

1 = Power up

(Note: RMIC must also be set to enable the

PGA)

MICB

MICBIAS

0 = Power down

1 = Power up

DIGENB

Master Clock Disable

0 = Master clock enabled

1 = Master clock disabled

R26 (1Ah)

Power

Management

(2)

DACL

DAC Left

0 = Power down

1 = Power up

DACR

DAC Right

0 = Power down

1 = Power up

LOUT1

LOUT1 Output Buffer

0 = Power down

1 = Power up

ROUT1

ROUT1 Output Buffer

0 = Power down

1 = Power up

SPKL

SPK_LP/SPK_LN Output PGA.

0 = Power down

1 = Power up

(Note: Speaker output also requires

SPK_OP_EN[0] to be set)

SPKR

SPK_RP/SPK_RN Output PGA

0 = Power down

1 = Power up

(Note: Speaker output also requires

SPK_OP_EN[1] to be set)

OUT3

OUT3 Output Buffer

0 = Power down

1 = Power up

WM8956CGEFL/V Datasheet(PDF) 57 Page - Wolfson Microelectronics plc

WM8956CGEFL/V Datasheet(HTML) 57 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL