UPSD3312D datasheet(193/272 Pages) STMICROELECTRONICS

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UPSD33xx

PSD module

Doc ID 9685 Rev 7

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the PSD module with JTAG. When set, the security bit will block access of JTAG

programming equipment from reading or modifying the PSD module Flash memory and

PLD configuration. The security bit also blocks JTAG access to the MCU module for

debugging. The only way to defeat the security bit is to erase the entire PSD module using

JTAG (erase is the only JTAG operation allowed while security bit is set), after which the

device is blank and may be used again. The 8032 MCU will always have access to Flash

memory contents through its 8-bit data bus even while the security bit is set. The 8032 can

read the status of the security bit at run-time (but it cannot change it) by reading the csiop

27.4.24

PLDs

The PSD module contains two PLDs: the Decode PLD (DPLD), and the General PLD

(GPLD), as shown in Figure 62 on page 195. Both PLDs are fed by a common PLD input

signal bus, and additionally, the GPLD is connected to the 8032 data bus.

PLD logic is specified using PSDsoft Express and programmed into the PSD module using

the JTAG ISP channel. PLD logic is non-volatile and available at power-up. PLDs may not be

programmed by the 8032. The PLDs have selectable levels of performance and power

consumption.

The DPLD performs address decoding, and generates select signals for internal and

external components, such as memory, registers, and I/O ports. The DPLD can generate

External Chip-Select (ECS1-ECS2) signals on Port D.

The GPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, encoding and decoding logic. These logic functions can be constructed

from a combination of 16 Output Macrocells (OMC), 20 Input Macrocells (IMC), and the

AND-OR Array.

Routing of the 16 OMCs outputs can be divided between pins on three Ports A, B, or C by

the OMC Allocator as shown in Figure 66 on page 202. Eight of the 16 OMCs that can be

routed to pins on Port A or Port B and are named MCELLAB0-MCELLAB7. The other eight

OMCs to be routed to pins on Port B or Port C and are named MCELLBC0-MCELLBC7.

This routing depends on the pin number assignments that are specified in PSDsoft Express

for “PLD Outputs” in the Pin Definition section. OMC outputs can also be routed internally

(not to pins) used as buried nodes to create shifters, counters, etc.

Table 119.

Main Flash Memory Protection register definition (address = csiop + offset C0h)(1)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot

Sec6_Prot

Sec5_Prot

Sec4_Prot

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Bit definitions:

Sec_Prot 1 = Flash memory sector is write protected, 0 = Flash memory sector is not write protected.

Table 120.

Secondary Flash Memory Protection/Security register Definition (csiop+offset C2h)(1)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Security_Bit

not used

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Security_Bit = 1, device is secured, 0 = not secured

Sec_Prot 1 = Flash memory sector is write protected, 0 = Flash memory sector is not write protected.

UPSD3312D Datasheet(PDF) 193 Page - STMicroelectronics

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