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UPSD3312D Datasheet(PDF) 197 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 197 Page - STMicroelectronics |
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197 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx PSD module Doc ID 9685 Rev 7 197/272 Figure 63. DPLD logic array FS0 FS1 FS7 FS6 FS5 FS4 FS3 FS2 MAIN FLASH MEMORY SECTOR SELECTS CSBOOT0 CSBOOT3 CSBOOT2 CSBOOT1 SECONDARY FLASH MEMORY SECTOR SELECTS RS0 SRAM SELECT CSIOP I/O & CONTROL REGISTERS SELECT ECS0 ECS1 EXTERNAL CHIP- SELECTS (PORT D) PSEL0 PSEL1 PERIPHERAL I/O MODE RANGE SELECTS 8032 ADDRESS (A0 - A15) 16 4 1 POWER-DOWN INDICATOR (PDN) 1 PIN INPUT PORTS A, B, C (IMCs) 20 PIN INPUT PORT D 2 OMC FEEDBACK (MCELLAB.FB0-7) 8 PAGE REGISTER (PGR0 - PGR7) 8 8 1 OMC FEEDBACK (MCELLBC.FB0-7) PLD INPUT BUS 3 3 3 3 3 3 3 3 3 3 3 3 2 1 1 1 1 1 NUMBER OF PRODUCT TERMS AI06601A PSM MODULE RESET (RST) FLASH MEM PROG STATUS (RDYBSY) 8032 CNTL (RD, WR, PSEN, ALE) |
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