UPSD3312D datasheet(198/272 Pages) STMICROELECTRONICS

Part #	UPSD3312D

Description	fast 8032 MCU with programmable logic

PDF	272 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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198 / 272 page

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PSD module

UPSD33xx

198/272

Doc ID 9685 Rev 7

27.4.27

General PLD (GPLD)

The GPLD is used to create general system logic. Figure 62 shows the architecture of the

entire GPLD, and Figure 64 shows the relationship between one OMC, one IMC, and one

I/O port pin, which is representative of pins on Ports A, B, and C. It is important to

understand how these elements work together. A more detailed description will follow for the

three major blocks (OMC, IMC, I/O Port) shown in Figure 64. Figure 64 also shows which

csiop registers to access for various PLD and I/O functions.

The GPLD contains:

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16 Output Macrocells (OMC)

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20 Input Macrocells (IMC)

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OMC Allocator

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Product Term Allocator inside each OMC

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AND-OR Array capable of generating up to 137 product terms

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Three I/O Ports, A, B, and C

UPSD3312D Datasheet(PDF) 198 Page - STMicroelectronics