UPSD3312D datasheet(203/272 Pages) STMICROELECTRONICS

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Table 122.

OMC port and data bit assignments

27.4.31

Loading and reading OMCs

Each of the two OMC groups (eight OMCs each) occupies a byte in csiop space, named

MCELLAB and MCELLBC (see Table 123 and Table 124 on page 204). When the 8032

writes or reads these two OMC registers in csiop it is accessing each of the OMCs through

it’s 8-bit data bus, with the bit assignment shown in Table 122 on page 203. Sometimes it is

important to know the bit assignment when the user builds GPLD logic that is accessed by

the 8032. For example, the user may create a 4-bit counter that must be loaded and read by

the 8032, so the user must know which nibble in the corresponding csiop OMC register the

firmware must access. The fitter report generated by PSDsoft Express will indicate how it

assigned the OMCs and data bus bits to the logic. The user can optionally force PSDsoft

Express to assign logic to specific OMCs and data bus bits if desired by using the

‘PROPERTY’ statement in PSDsoft Express. Please see the PSDsoft Express User’s

Manual for more information on OMC assignments.

Loading the OMC flip-flops with data from the 8032 takes priority over the PLD logic

functions. As such, the preset, clear, and clock inputs to the flip-flop can be asynchronously

overridden when the 8032 writes to the csiop registers to load the individual OMCs.

OMC

Port

assignment

(1)(2)

MCELLAB0-MCELLAB7 can be output to Port A pins only on 80-pin devices. Port A is not available on 52-

pin devices

Port pins PC0, PC1, PC5, and PC6 are dedicated JTAG pins and are not available as outputs for

MCELLBC 0, 1, 5, or 6

Native Product

terms from AND-

OR array

Maximum

borrowed product

terms

Data bit on 8032

data bus for

loading or reading

OMC

MCELLAB0

Port A0 or B0

MCELLAB1

Port A1 or B1

MCELLAB2

Port A2 or B2

MCELLAB3

Port A3 or B3

MCELLAB4

Port A4 or B4

MCELLAB5

Port A5 or B5

MCELLAB6

Port A6 or B6

MCELLAB7

Port A7 or B7

MCELLBC0

Port B0

MCELLBC1

Port B1

MCELLBC2

Port B or C2

MCELLBC3

Port B3 or C3

MCELLBC4

Port B4 or C4

MCELLBC5

Port B5

MCELLBC6

Port B6

MCELLBC7

Port B7 orC7

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