UPSD3312D datasheet(206/272 Pages) STMICROELECTRONICS

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PSD module

UPSD33xx

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Doc ID 9685 Rev 7

27.4.34

I/O ports

There are four programmable I/O ports on the PSD module: Port A (80-pin device only), Port

B, Port C, and Port D. Ports A and B are eight bits each, Port C is four bits, and Port D is two

bits for 80-pin devices or 1-bit for 52-pin devices. Each port pin is individually configurable,

thus allowing multiple functions per port. The ports are configured using PSDsoft Express

then programming with JTAG, and also by the 8032 writing to csiop registers at run-time.

Topics discussed in this section are:

●

General Port architecture

●

Port Operating modes

●

Individual Port Structure

27.4.35

General port architecture

The general architecture for a single I/O Port pin is shown in Figure 68 on page 208. Port

structures for Ports A, B, C, and D differ slightly and are shown in Figure 73 on page 219

though Figure 76 on page 223.

Figure 68 on page 208 shows four csiop registers whose outputs are determined by the

value that the 8032 writes to csiop Direction, Drive, Control, and Data Out. The I/O Port logic

contains an output mux whose mux select signal is determined by PSDsoft Express and the

csiop Control register bits at run-time. Inputs to this output mux include the following:

Data from the csiop Data Out register for MCU I/O output mode (All ports)

Latched de-multiplexed 8032 Address for Address Output mode (Ports A and B only)

Peripheral I/O mode data bit (Port A only)

GPLD OMC output (Ports A, B, and C).

Table 127.

Input Macrocell Port A (address = csiop + offset 0Ah)(1)(2)

Port A not available on 52-pin UPSD33xx devices

1 = current state of IMC is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IMC PA7

IMC PA6

IMC PA5

IMC PA4

IMC PA3

IMC PA2

IMC PA1

IMC PA0

Table 128.

Input Macrocell Port B (address = csiop + offset 0Bh)(1)

1 = current state of IMC is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IMC PB7

IMC PB6

IMC PB5

IMC PB4

IMC PB3

IMC PB2

IMC PB1

IMC PB0

Table 129.

Input Macrocell Port C (address = csiop + offset 18h)(1)(2)

X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins.

1 = current state of IMC is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IMC PC7

IMC PC4

IMC PC3

IMC PC2

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