UPSD3312D datasheet(208/272 Pages) STMICROELECTRONICS

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UPSD33xx

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Doc ID 9685 Rev 7

Figure 68.

Detail of a single I/O port (typical of Ports A, B, C)

Table 130.

Port operating modes

I/O PORT

LOGIC

DIRECTION

DRIVE SELECT

CONTROL

DATA OUT (MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

D BIT, PERIPH I/O MODE, Port A

PT OUTPUT ENABLE (.OE)

LATCHED ADDR BIT, PORT A or B

MUX

8032

DATA

BIT

OUTPUT

DRIVER

TYPICAL

PORT A, B, C

PSD MODULE RESET

ONE of 6

CSIOP

REGISTERS

OUTPUT

SELECT

PERIPHERAL I/O

MODE SETS

DIRECTION

(PORT A ONLY)

FROM OMC OUTPUT

TO IMC

FROM PLD INPUT BUS

FROM AND-OR ARRAY

FROM OMC

ALLOCATOR

CLR

DIRECTION

DRIVE

CONTROL

(MCUI/O)

DATA OUT

RESET

PSDsoft

PSELx

PERIPH I/O

DATA BIT

CSIOP

REGIS-

TERS

DRIVE TYPE

8032

DATA

BITS

INPUT

BUFFER

OUTPUT ENABLE

RD PIO EN

8032

8032 RD

AI07873A

Port operating mode

Port A (80-pin

only)

Port B

Port C

Port D

Find it

MCU I/O

Yes

Section 27.4.37

PLD I/O

OMC MCELLAB Outputs

OMC MCELLBC Outputs

External Chip-Select Outputs

PLD Inputs

Yes

Yes(1)

Yes

MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.

Yes

Section 27.4.38

Latched Address Output

Yes

Section 27.4.39

Peripheral I/O mode

Yes

Section 27.4.40

JTAG ISP

Yes(2)

JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions (cannot be

used for general I/O).

Note 27.4.41

on page 216

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