UPSD3312D datasheet(210/272 Pages) STMICROELECTRONICS

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PSD module

UPSD33xx

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Doc ID 9685 Rev 7

Table 132.

MCU I/O Mode Port A Data In register (address = csiop + offset 00h)(1)(2)

Port A not available on 52-pin UPSD33xx devices

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Table 133.

MCU I/O Mode Port B Data In register (address = csiop + offset 01h)(1)

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Table 134.

MCU I/O Mode Port C Data In register (address = csiop + offset 10h)(1)(2)

X = Not guaranteed value, can be read either '1' or '0.'

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7

PC4

PC3

PC2

Table 135.

MCU I/O Mode Port D Data Inregister (address = csiop + offset 11h)(1)(2)

X = Not guaranteed value, can be read either '1' or '0.'

For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

XXX

PD2(3)

Not available on 52-pin UPSD33xx devices

PD1

Table 136.

MCU I/O Mode Port A Data Out register (address =csiop+offset 04h)(1)(2)(3)

Port A not available on 52-pin UPSD33xx devices

For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’

Default state of register is 00h after reset or power-up

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Table 137.

MCU I/O Mode Port B Data Out register (address = csiop + offset 05h)(1)(2)

For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’

Default state of register is 00h after reset or power-up

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

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