UPSD3312D datasheet(209/272 Pages) STMICROELECTRONICS

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UPSD33xx

PSD module

Doc ID 9685 Rev 7

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Table 131.

Port configuration setting requirements

27.4.37

MCU I/O mode

In MCU I/O mode, the 8032 on the MCU module expands its own I/O by using the I/O Ports

on the PSD module. The 8032 can read PSD module I/O pins, set the direction of the I/O

pins, and change the output state of I/O pins by accessing the Data In, Direction, and Data

Out csiop registers respectively at run-time.

To implement MCU I/O mode, each desired pin is specified in PSDsoft Express as MCU I/O

function and given a pin name. Then 8032 firmware is written to set the Direction bit for each

corresponding pin during initialization routines (0 = In, 1 = Out of the chip), then the 8032

firmware simply reads the corresponding Data In register to determine the state of an I/O

pin, or writes to a Data Out register to set the state of a pin. The Direction of each pin may

be changed dynamically by the 8032 if desired. A mixture of input and output pins within a

single port is allowed. Figure 68 on page 208 shows the Data In, Data Out, and Direction

signal paths.

The Data In registers are defined in Table 132 to Table 135 on page 210. The Data Out

registers are defined in Table 136 to Table 139 on page 211. The Direction registers are

defined in Table 140 to Table 27.4.38 on page 212.

Port

operating

mode

Required action in

PSDsoft Express to

configure each pin

Value that 8032

writes to csiop

Control register

at run-time

Value that 8032

writes to csiop

Direction

time

Value that 8032

writes to bit 7

(PIO_EN) of csiop

VM register at run-

time

MCU I/O

Choose the MCU I/O

function and declare

the pin name

Logic '0' (default)

Logic 1 = Out of

UPSD

Logic 0 = Into

UPSD

N/A

PLD I/O

Choose the PLD

function type, declare

pin name, and specify

logic equation(s)

N/A

Direction register

has no effect on a

pin if pin is driven

from OMC output

N/A

Latched

Address Output

Choose Latched

Address Out function,

declare pin name

Logic '1'

Logic '1' Only

N/A

Peripheral I/O

Choose Peripheral

I/O mode function

and specify address

range in DPLD for

PSELx

N/A

PIO_EN Bit = Logic

(default is '0')

4-PIN JTAG ISP

No action required in

PSDsoft to get 4-pin

JTAG. By default

TDO, TDI, TCK, TMS

are dedicated JTAG

functions.

N/A

6-PIN JTAG ISP

(faster

programming)

Choose JTAG TSTAT

function for pin PC3

and JTAG TERR

function for pin PC4.

N/A

UPSD3312D Datasheet(PDF) 209 Page - STMicroelectronics

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