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UPSD3312D Datasheet(PDF) 207 Page - STMicroelectronics

Part # UPSD3312D
Description  fast 8032 MCU with programmable logic
PDF  272 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3312D Datasheet(HTML) 207 Page - STMicroelectronics

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Doc ID 9685 Rev 7
207/272
The Port Data Buffer (PDB) provides feedback to the 8032 and allows only one source at a
time to be read when the 8032 reads various csiop registers. There is one PDB for each port
pin enabling the 8032 to read the following on a pin-by-pin basis:
1.
MCU I/O signal direction setting (csiop Direction reg)
2.
Pin drive type setting (csiop Drive Select reg)
3.
Latched Addr Out mode setting (csiop Control reg)
4.
MCU I/O pin output setting (csiop Data Out reg)
5.
Output Enable of pin driver (csiop Enable Out reg)
6.
MCU I/O pin input (csiop Data In reg)
A port pin’s output enable signal is controlled by a two input OR gate whose inputs come
from: a product term of the AND-OR array; the output of the csiop Direction register. If an
output enable from the AND-OR Array is not defined, and the port pin is not defined as an
OMC output, and if Peripheral I/O mode is not used, then the csiop Direction register has
sole control of the OE signal.
As shown in Figure 68 on page 208, a physical port pin is connected to the I/O Port logic
and is also separately routed to an IMC, allowing the 8032 to read a port pin by two different
methods (MCU I/O input mode or read the IMC).
27.4.36
Port operating modes
I/O Port logic has several modes of operation. Table 125 on page 204 summarizes which
modes are available on each port. Each of the port operating modes are described in
following sections. Some operating modes can be defined using PSDsoft Express, and
some by the 8032 writing to the csiop registers at run-time, and some require both. For
example, PLD I/O, Latched Address Out, and Peripheral I/O modes must be defined in
PSDsoft Express and programmed into the device using JTAG, but an additional step must
happen at run-time to activate Latched Address Out mode and Peripheral I/O mode, but not
needed for PLD I/O. In another example, MCU I/O mode is controlled completely by the
8032 at run-time and only a simple pin name declaration is needed in PSDsoft Express for
documentation.
Table 131 on page 209 summarizes what actions are needed in PSDsoft Express and what
actions are required by the 8032 at run-time to achieve the various port functions.



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