UPSD3312D datasheet(204/272 Pages) STMICROELECTRONICS

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Doc ID 9685 Rev 7

27.4.32

OMC Mask registers

There is one OMC Mask register for each of the two groups of eight OMCs shown in

Table 125 and Table 126. The OMC mask registers are used to block loading of data to

individual OMCs. The default value for the mask registers is 00h, which allows loading of all

OMCs. When a given bit in a mask register is set to a '1,' the 8032 is blocked from writing to

the associated OMC flip-flop. For example, suppose that only four of eight OMCs

(MCELLAB0-3) are being used for a state machine. The user may not want the 8032 write to

all the OMCs in MCELLAB because it would overwrite the state machine registers.

Therefore, the user would want to load the mask register for MCELLAB with the value 0Fh

before writing OMCs.

Table 123.

Output Macrocell MCELLAB (address = csiop + offset 20h)(1)

All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on

reset)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCELLAB

Table 124.

Output Macrocell MCELLAC (address = csiop + offset 21h)(1)

All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on

reset)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCELLBC

Table 125.

Output Macrocell MCELLAB Mask register (address = csiop + offset

22h)(1)(2)

Default is 00h after any reset condition;

1 = block writing to individual macrocell, 0 = allow writing to individual macrocell

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mask

MCELLAB

Mask

MCELLAB

Mask

MCELLAB

Mask

MCELLAB

Mask

MCELLAB

Mask

MCELLAB

Mask

MCELLAB

Mask

MCELLAB

Table 126.

Output Macrocell MCELLBC Mask register (address = csiop + offset

23h)(1)(2)

Default is 00h after any reset condition;

1 = block writing to individual macrocell, 0 = allow writing to individual macrocell

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mask

MCELLBC

Mask

MCELLBC

Mask

MCELLBC

Mask

MCELLBC

Mask

MCELLBC

Mask

MCELLBC

Mask

MCELLBC

Mask

MCELLBC

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