UPSD3312D datasheet(270/272 Pages) STMICROELECTRONICS

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Important notes

UPSD33xx

270/272

Doc ID 9685 Rev 7

Important notes

The following sections describe the limitations that apply to the UPSD33xx devices.

33.1

PORT 1 not 5 V I/O tolerant

Description

The port P1 is shared with the ADC module and as a result Port P1 is not 5 V tolerant.

Impact on application

5 V devices should not be connected to port P1.

Workaround

Peripherals or GPIO that require 5 V I/O tolerance should be mapped to Port 3 or Port 4.

33.2

9th received data bit corrupted in UART modes 2 and 3

Description

If the 9th transmit data bit is written by firmware into TB8 at the same time as a received 9th

bit is being written by the hardware into RB8, RB8 is not correctly updated. This applies to

both UART0 and UART1. Typically, the 9th data bit is used as a parity bit to check for data

transmission errors on a byte by byte basis.

Impact on application

UART modes 2 and 3 can't be used reliably in full-duplex mode.

Workaround

Some options include:

Only use mode 1 (8 data bits) for full-duplex communication.

Use mode 1 and a packet based communication protocol with a checksum or CRC to

detect data transmission errors.

Use UART0 in mode 2 or 3 for transmitting data and UART1 in mode 2 or 3 for

receiving data.

Use some form of handshaking to ensure that data is never transmitted and received

simultaneously on a single UART configured in mode 2 or 3.

UPSD3312D Datasheet(PDF) 270 Page - STMicroelectronics