CP3SP33SMSSLASHNOPB datasheet(332/407 Pages) TI1

332 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

TEN

The Timer Enable bit controls whether the Multi-Function Timer is enabled. When the module

is disabled all clocks to the counter unit are stopped to minimize power consump- tion. For

that reason, the timer/counter registers (TCNT1_n and TCNT2_n), the capture/ reload

registers (TCRA_n and TCRB_n), and the interrupt pending bits (TXPND) cannot be written in

this mode. Also, the 5-bit clock prescaler and the interrupt pending bits are cleared, and the

TAn I/O pin is an input.

0 – Multi-Function Timer is disabled.

1 – Multi-Function Timer is enabled.

32.5.8 Timer Interrupt Control Register n (TICTL_n)

The TICTL_n register is a byte-wide, read/write register that contains the interrupt enable bits and interrupt

pending bits for the four timer interrupt sources, designated A, B, C, and D. The condition that causes

each type of interrupt depends on the operating mode, as shown in Table 32-1.

This register is cleared upon reset. The register format is shown below.

TDIEN

TCIEN

TBIEN

TAIEN

TDPND

TCPND

TBPND

TAPND

The Timer Interrupt Source A Pending bit indicates that timer interrupt condition A has

occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 32-1. This bit

can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt

Clear Register (TICLR_n). Attempting to directly write a 0 to this bit is ignored.

0 – Interrupt source A has not triggered.

1 – Interrupt source A has triggered.

TBPND

The Timer Interrupt Source B Pending bit indicates that timer interrupt condition B has

occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 32-1. This bit

can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt

Clear Register (TICLR_n). Attempting to directly write a 0 to this bit is ignored.

0 – Interrupt source B has not triggered.

1 – Interrupt source B has triggered.

TCPND

The Timer Interrupt Source C Pending bit indicates that timer interrupt condition C has

occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 32-1. This bit

can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt

Clear Register (TICLR_n). Attempting to directly write a 0 to this bit is ignored.

0 – Interrupt source C has not triggered.

1 – Interrupt source C has triggered.

TDPND

The Timer Interrupt Source D Pending bit indicates that timer interrupt condition D has

occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 32-1. This bit

can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt

Clear Register (TICLR_n). Attempting to directly write a 0 to this bit is ignored.

0 – Interrupt source D has not triggered.

1 – Interrupt source D has triggered.

TAIEN

The Timer Interrupt A Enable bit controls whether an interrupt is asserted on each occurrence

of interrupt condition A. For an explanation of interrupt conditions A, B, C, and D, see

Table 32-1.

0 – Condition A interrupts disabled.

1 – Condition A interrupts enabled.

TBIEN

The Timer Interrupt B Enable bit controls whether an interrupt is asserted on each occurrence

of interrupt condition B. For an explanation of interrupt conditions A, B, C, and D, see

Table 32-1.

– Condition B interrupts disabled.

1 – Condition B interrupts enabled.

332

Dual Multi-Function Timers

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB Datasheet(PDF) 332 Page - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 332 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL