CP3SP33SMSSLASHNOPB datasheet(333/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

TCIEN

The Timer Interrupt C Enable bit controls whether an interrupt is asserted on each occurrence

of interrupt condition C. For an explanation of interrupt conditions A, B, C, and D, see

Table 32-1.

0 – Condition C interrupts disabled.

1 – Condition C interrupts enabled.

TDIEN

The Timer Interrupt D Enable bit controls whether an interrupt is asserted on each occurrence

of interrupt condition D. For an explanation of interrupt conditions A, B, C, and D, see

Table 32-1.

0 – Condition D interrupts disabled.

1 – Condition D interrupts enabled.

32.5.9 Timer Interrupt Clear Register n (TICLR_n)

The TICLR_n register is a byte-wide, write-only register that allows software to clear the TAPND, TBPND,

TCPND, and TDPND bits in the Timer Interrupt Control (TICTL_n) register. Do not modify this register with

instructions that access the register as a read-modify-write operand, such as the bit manipulation

instructions. The register reads as FFh. The register format is shown below.

Reserved

TDCLR

TCCLR

TBCLR

TACLR

The Timer Pending A Clear bit is used to clear the Timer Interrupt Source A Pending bit

(TAPND) in the Timer Interrupt Control regi ter (TICTL).

0 – Writing a 0 has no effect.

1 – Writing a 1 clears the TAPND bit.

TBCLR

The Timer Pending A Clear bit is used to clear the Timer Interrupt Source B Pending bit (TB-

PND) in the Timer Interrupt Control register (TICTL).

0 – Writing a 0 has no effect.

1 – Writing a 1 clears the TBPND bit.

TCCLR

The Timer Pending C Clear bit is used to clear the Timer Interrupt Source C Pending bit

(TCPND) in the Timer Interrupt Control register (TICTL_n).

0 – Writing a 0 has no effect.

1 – Writing a 1 clears the TCPND bit.

TDCLR

The Timer Pending D Clear bit is used to clear the Timer Interrupt Source D Pending bit (TD-

PND) in the Timer Interrupt Control register (TICTL_n).

0 – Writing a 0 has no effect.

1 – Writing a 1 clears the TDPND bit.

Dual Multi-Function Timers

333

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