CP3SP33SMSSLASHNOPB datasheet(338/407 Pages) TI1

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COUNT1_n[15:0]

Restart

[15:0]

P2POL

TIOn_2

PERCAP1_n[15:0]

Compare

DTYCAP1_n[15:0]

Compare

C1PRSC

= =

Prescaler

Counter

P1POL

TIOn_1

TMOD1 = 10

T1RUN

DS356

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 33-4. VTU 1-bit PWM Mode

33.1.3 Dual 16-Bit Capture Mode

In addition to the two PWM modes, each timer subsystem may be configured to operate in an input

capture mode which provides two 16-bit capture channels. The input capture mode can be used to

precisely measure the period and duty cycle of external signals.

In capture mode the counter COUNTx_n operates as a 16- bit up-counter while the two TIOn_y pins

associated with a timer subsystem operate as capture inputs. A capture event on the TIOn_y pins causes

the contents of the counter register (COUNTx_n) to be copied to the PERCAPx_n or DTYCAPx_n

registers, respectively.

Starting the counter is identical to the 16-bit PWM mode, i.e., setting the lower of the two MODE_n.TxRUN

bits will start the counter and the clock prescaler. In addition, the capture event inputs are enabled once

the MODE_n.TxRUN bit is set.

The TIOn_y capture inputs can be independently configured to detect a capture event on either a positive

transition, a negative transition or both a positive and a negative transition. In addition, any capture event

may be used to reset the counter COUNTx_n and the clock prescaler counter. This avoids the need for

software to keep track of timer overflow conditions and greatly simplifies the direct frequency and duty

cycle measurement of an external signal.

Figure 33-5 illustrates the configuration of a timer subsystem while operating in capture mode. The

numbering in Figure 33-5 refers to timer subsystem 1 but equally applies to the other three timer

subsystems.

338

Dual Versatile Timer Units (VTU)

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