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CP3SP33SMS/NOPB Datasheet(PDF) 340 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 340 Page - Texas Instruments |
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340 / 407 page  System Interrupt Request 1 I1AEN I1BEN I1CEN I1DEN I1APD I1BPD I1CPD I1DPD System Interrupt Request 4 I4AEN I4BEN I4CEN I4DEN I4APD I4BPD I4CPD I4DPD DS093 CP3SP33 SNOSCW5 – MAY 2013 www.ti.com Figure 33-6. VTU Interrupt Request Structure Each of the timer pending bits, IxAPD through IxDPD, is set by a specific hardware event depending on the mode of operation, i.e., PWM or Capture mode. Table 33-1 outlines the specific hardware events relative to the operation mode which cause an interrupt pending bit to be set. Table 33-1. VTU Interrupt Sources PENDING FLAG DUAL 8-BIT PWM MODE 16-BIT PWM MODE CAPTURE MODE IxAPD Low Byte Duty Cycle match Duty Cycle match Capture to PERCAPx_n IxBPD Low Byte Period match Period match Capture to DTYCAPx_n IxCPD High Byte Duty Cycle match N/A Counter Overflow IxDPD High Byte Period match N/A N/A 33.1.6 Freeze Mode If Freeze is mode is entered, all timer counter clocks will be inhibited and the current value of the timer registers will be frozen; in capture mode, all further capture events are disabled. Once Freeze mode is exited, counting will resume from the previous value and the capture input events are reenabled. 33.2 VTU Registers Each of the two VTUs has a total of 19 user-accessible registers, as listed in Table 33-2. All registers are word-wide and are initialized to a known value upon reset. All software accesses to the VTU registers must be word accesses. Table 33-2. VTU Registers NAME ADDRESS DESCRIPTION MODE_0 FF 8800h Mode Control Register Module 0 MODE_1 FF 8C00h Mode Control Register Module 1 340 Dual Versatile Timer Units (VTU) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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