CP3SP33SMSSLASHNOPB datasheet(339/407 Pages) TI1

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COUNT1_n[15:0]

Restart

15:0

C1EDG

PERCAP1_n[15:0]

Compare

DTYCAP1_n[15:0]

Compare

C1PRSC

= =

Prescaler

Counter

rst

cap

TMOD1=11

T1RUN

C2EDG

TIOn_2

rst

cap

DS357

TIOn_1

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Figure 33-5. VTU Dual 16-Bit Capture Mode

33.1.4 Low Power Mode

If a timer subsystem is not used, software can place it in a low-power mode. All clocks to a timer

subsystem are stopped and the counter and prescaler contents are frozen once low-power mode is

entered. Software may continue to write to the MODE_n, INTCTL_n, IOxCTL_n, and CLKxPS_n registers.

Write operations to the INTPND_n register are allowed; but if a timer subsystem is in low-power mode, its

associated interrupt pending bits cannot be cleared. Software cannot write to the COUNTx_n,

PERCAPx_n, and DTYCAPx_n registers of a timer subsystem while it is in low-power mode. All registers

can be read at any time.

33.1.5 Interrupts

Each VTU has a total of 16 interrupt sources, four for each of the four timer subsystems. All interrupt

sources have a pending bit and an enable bit associated with them. All interrupt pending bits are denoted

IxAPD through IxDPD where “x” relates to the specific timer subsystem. There is one system level

interrupt request for each of the four timer subsystems.

Figure 33-6 illustrates the interrupt structure of the versatile timer module.

Dual Versatile Timer Units (VTU)

339

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