CP3SP33SMSSLASHNOPB datasheet(343/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

P6POL

C8EDG

P7POL

C7EDG

P6POL

C6EDG

P5POL

C5EDG

The functionality of the bit fields of the IO2CTL_n register is identical to the ones described in the

IO1CTL_n register section.

33.2.4 Interrupt Control Register Module n (INTCTL_n)

The INTCTL_n registers are 16-bit, read/write registers. They contain the interrupt enable bits for the 16

interrupt sources of each VTU. Each interrupt enable bit corresponds to an interrupt pending bit located in

the Interrupt Pending Register (INTPND_n). All INTCTL_n register bits are solely under software control.

The registers are clear after reset.

I2DEN

I2CEN

I2BEN

I2AEN

I1DEN

I1CEN

I1BEN

I1AEN

I4DEN

I4CEN

I4BEN

I4AEN

I3DEN

I3CEN

I3BEN

I3AEN

IxAEN

The Timer x Interrupt A Enable bit controls interrupt requests triggered on the corresponding

IxAPD bit being set. The associated IxAPD bit will be updated regardless of the value of the

IxAEN bit.

0 – Disable system interrupt request for the IxAPD pending bit.

1 – Enable system interrupt request for the IxAPD pending bit.

IxBEN

The Timer x Interrupt B Enable bit controls interrupt requests triggered on the corresponding

IxBPD bit being set. The associated IxBPD bit will be updated regardless of the value of the

IxBEN bit.

0 – Disable system interrupt request for the IxBPD pending bit.

1 – Enable system interrupt request for the IxBPD pending bit.

IxCEN The Timer x Interrupt C Enable bit controls interrupt requests triggered on the corresponding

IxCPD bit being set. The associated IxCPD bit will be updated regardless of the value of the

IxCEN bit.

0 – Disable system interrupt request for the IxCPD pending bit.

1 – Enable system interrupt request for the IxCPD pending bit.

IxDEN Timer x Interrupt D Enable bit controls interrupt requests triggered on the corresponding IxDPD

bit being set. The associated IxDPD bit will be updated regardless of the value of the IxDEN bit.

0 – Disable system interrupt request for the IxDPD pending bit.

1 – Enable system interrupt request for the IxDPD pending bit.

33.2.5 Interrupt Pending Register Module n (INTPND_n)

The INTPND_n registers are 16-bit, read/write registers which contain all 16 interrupt pending bits. There

are four interrupt pending bits called IxAPD through IxDPD for each timer subsystem. Each interrupt

pending bit is set by a hardware event and can be cleared if software writes a 1 to the bit position. The

value will remain unchanged if a 0 is written to the bit position. All interrupt pending bits are cleared at

reset.

I2DPD

I2CPD

I2BPD

I2APD

I1DPD

I1CPD

I1BPD

I1APD

I4DPD

I4CPD

I4BPD

I4APD

I3DPD

I3CPD

I3BPD

I3APD

Dual Versatile Timer Units (VTU)

343

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