CP3SP33SMSSLASHNOPB datasheet(344/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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IxAPD

The Timer x Interrupt A Pending bit indicates that an interrupt condition for the related timer

subsystem has occurred. Table 33-1 lists the hardware condition which causes this bit to be set.

0 – No interrupt pending.

1 – Timer interrupt condition occurred.

IxBPD

The Timer x Interrupt B Pending bit indicates that an interrupt condition for the related timer

subsystem has occurred. Table 33-1 lists the hardware condition which causes this bit to be set.

0 – No interrupt pending.

1 – Timer interrupt condition occurred.

IxCPD The Timer x Interrupt C Pending bit indicates that an interrupt condition for the related timer

subsystem has occurred. Table 33-1 lists the hardware condition which causes this bit to be set.

0 – No interrupt pending.

1 – Timer interrupt condition occurred.

IxDPD The Timer x Interrupt D Pending bit indicates that an interrupt condition for the related timer

subsystem has occurred. Table 33-1 lists the hardware condition which causes this bit to be set.

0 – No interrupt pending.

1 – Timer interrupt condition occurred.

33.2.6 Clock Prescaler Register 1 Module n (CLK1PS_n)

The CLK1PS_n registers are 16-bit, read/write registers. The registers are split into two 8-bit fields called

C1PRSC and C2PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 1

and 2 respectively. The registers are cleared at reset.

8M M7

C2PRSC

C1PRSC

C1PRSC The Clock Prescaler 1 Compare Value field holds the 8-bit prescaler value for timer sub-

system 1. The counter of timer subsystem is incremented each time when the clock prescaler

compare value matches the value of the clock prescaler counter. The division ratio is equal to

(C1PRSC + 1). For example, 00h is a ratio of 1, and FFh is a ratio of 256.

C2PRSC The Clock Prescaler 2 Compare Value field holds the 8-bit prescaler value for timer sub-

system 2. The counter of timer subsystem is incremented each time when the clock prescaler

compare value matches the value of the clock prescaler counter. The division ratio is equal to

(C2PRSC + 1).

33.2.7 Clock Prescaler Register 2 Module n (CLK2PS_n)

The CLK2PS_n registers are 16-bit, read/write registers. The registers are split into two 8-bit fields called

C3PRSC and C4PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 3

and 4 respectively. The registers are cleared at reset.

8M M7

C3PRSC

C4PRSC

C4PRSC The Clock Prescaler 3 Compare Value field holds the 8-bit prescaler value for timer sub-

system 3. The counter of timer subsystem is incremented each time when the clock prescaler

compare value matches the value of the clock prescaler counter. The division ratio is equal to

(C3PRSC + 1).

C3PRSC The Clock Prescaler 4 Compare Value field holds the 8-bit prescaler value for timer sub-

system 4. The counter of timer subsystem is incremented each time when the clock prescaler

compare value matches the value of the clock prescaler counter. The division ratio is equal to

(C4PRSC + 1).

344

Dual Versatile Timer Units (VTU)

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