SPC564A80L7 datasheet(151/157 Pages) STMICROELECTRONICS

151 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Document revision history

Doc ID 15399 Rev 9

151/157

02-Apr-2010

(cont)

Added information to AC timings section:

– New section added: Reset and configuration pin timing

– New section added: External interrupt timing (IRQ pin)

– New section added: eTPU timing

– Added Nexus debug port operating frequency table to Nexus timings section

– Added external bus interface maximum operating frequency table and calibration

bus interface maximum operation frequency table

– Added FlexCAN system clock source section

Changes to Power management control (PMC) and power on reset (POR) electrical

specifications:

– Max value for parameter 2 (vddreg) is 5.25 V (was 5.5 V)

Updated “Core voltage regulator controller external components preferred

configuration” diagram.

Changes to DC electrical specifications table:

– Slew rate on power supply pins (system requirement) changed to 25 V/ms (was

50 V/ms)

Throughout the document the maximum frequency is now 150 MHz (was 145 MHz)

Changes to DC electrical specifications:

– Parameter classifications added

–VDDREG max value changed to 5.25 V (was 5.5 V)

–VOH_LS min value changed to 2.0 V (was 2.7 V) with a load current of 0.5 mA

–VOL_LS max value changed to 0.6 V (was 0.2*VDDEH) with load current of 2 mA

–VINDC min value changed to VSSA-0.3 (was VSSA-1.0)

–VINDC max value changed to VDDA+0.3 (was VDDA+1.0)

Added new section: Configuring SRAM wait states

– VRCCTL external circuit updated.

01-Oct-2010

Updates to Nexus timings:

–tMDOV max value changed to 0.35 (was 0.2)

–tMSEOV max value changed to 0.35 (was 0.2)

–tEVTOV max value changed to 0.35 (was 0.2)

Updates to DC electrical specifications:

–VSTBY min value changed to 0.95 V (was 0.9 V)

–VSTBY has two ranges—for regulated mode and unregulated mode

Correction to PLLMRFM electrical specifications:

–VDDPLL range is from 1.08 V to 3.6 V (was 3.0 V to 3.6 V.

Updates to pad AC specifications:

– Specs with drive load = 200 pF deleted. DSC (drive strength control) values range

from 10–50pF.

– I/O pad average IDDE specifications updated (fast pad specs only)

– I/O pad VRC33 average IDDE specifications (fast pad specs only)

Updates to Reset and configuration pin timings:

– Footnote added: RESET pulse width is measured from 50% of the falling edge to

50% of the rising edge.

– Timings are specified at VDD = 1.14 V to 1.32 V (was 1.08 V to 1.32 V).

Table 56.

Revision history (continued)

Date

Revision

Changes

SPC564A80L7 Datasheet(PDF) 151 Page - STMicroelectronics

SPC564A80L7 Datasheet(HTML) 151 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL