S25FL002D0FMAI011 datasheet(7/38 Pages) SPANSION

7 / 38 page

June 9, 2004 30167A+1

S25FL Family (Serial Peripheral Interface)

Pre limin ary

I n f o r m a t ion

Signal Description

Signal Data Output (SO): This output signal is used to transfer data serially out

of the device. Data is shifted out on the falling edge of Serial Clock (SCK).

Serial Data Input (SI): This input signal is used to transfer data serially into

the device. It receives instructions, addresses, and the data to be programmed.

Values are latched on the rising edge of Serial Clock (SCK).

Serial Clock (SCK): This input signal provides the timing of the serial interface.

Instructions, addresses, and data present at the Serial Data input (SI) are latched

on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes

after the falling edge of Serial Clock (SCK).

Chip Select (CS#): When this input signal is High, the device is deselected and

Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase

or Write Status Register cycle is in progress, the device will be in Standby mode.

Driving Chip Select (CS#) Low enables the device, placing it in the active power

mode.

After Power-up, a falling edge on Chip Select (CS#) is required prior to the start

of any instruction.

Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communi-

cations with the device without deselecting the device.

During the Hold instruction, the Serial Data Output (SO) is high impedance, and

Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (CS#)

driven Low.

Write Protect (W#): The main purpose of this input signal is to freeze the size

of the area of memory that is protected against program or erase instructions (as

specified by the values in the BP1 and BP0 bits of the Status Register).

SPI Modes

These devices can be driven by a micro controller with its SPI peripheral running

in either of the two following modes:

CPOL = 0, CPHA = 0

CPOL = 1, CPHA = 1

For these two modes, input data is latched in on the rising edge of Serial Clock

(SCK), and output data is available from the falling edge of Serial Clock (SCK).

The difference between the two modes, as shown in Figure 2, is the clock polarity

when the bus master is in Standby and not transferring data:

SCK remains at 0 for (CPOL = 0, CPHA = 0)

SCK remains at 1 for (CPOL = 1, CPHA = 1)

S25FL002D0FMAI011 Datasheet(PDF) 7 Page - SPANSION