June 9, 2004 30167A+1

S25FL Family (Serial Peripheral Interface)

17

Pre limin ary

I n f o r m a t ion

Table 6. Protection Modes

5. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1 and

Table 2.

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its

initial delivery state), it is possible to write to the Status Register provided that

the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction, regardless of the whether Write Protect (W#) is driven High

or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set

to 1, two cases need to be considered, depending on the state of Write Protect

(W#):

If Write Protect (W#) is driven High, it is possible to write to the Status Reg-

ister provided that the Write Enable Latch (WEL) bit has previously been set

by a Write Enable (WREN) instruction.

If Write Protect (W#) is driven Low, it is not possible to write to the Status

Register even if the Write Enable Latch (WEL) bit has previously been set by

a Write Enable (WREN) instruction. (Attempts to write to the Status Register

are rejected, and are not accepted for execution). As a consequence, all the

data bytes in the memory area that are software protected (SPM) by the

Block Protect (BP1, BP0) bits of the Status Register, are also hardware pro-

tected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM)

can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write

Protect (W#) Low

or by driving Write Protect (W#) Low after setting the Status Register Write

Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull

Write Protect (W#) High.

If Write Protect (W#) is permanently tied High, the Hardware Protected Mode

(HPM) can never be activated, and only the Software Protected Mode (SPM),

using the Block Protect (BP1, BP0) bits of the Status Register, can be used.

Read Data Bytes (READ)

The device is first selected by driving Chip Select (CS#) Low. The instruction code

for the Read Data Bytes (READ) instruction is followed by a 3-byte address (ad-

dress bits A23 to A18 are Don’t Care), each bit being latched-in during the rising

edge of Serial Clock (SCK). Then the memory contents, at that address, are

W# Signal SRWD Bit

Mode

Write Protection of the Status

Register

Protected Area

(Note 1)

Unprotected Area

(Note 1)

1

1

Software

Protected

(SPM)

Status Register is Writeable (if the

WREN instruction has set the WEL

bit)

The values in the SRWD, BP1 and

BP0 bits can be changed

Protected against Page

Program and Erase

(SE, BE)

Ready to accept Page

Program and Sector

Erase Instructions

1

0

0

0

0

1

Hardware

Protected

(HPM)

Status Register is Hardware write

protected

The values in the SRWD, BP1 and

BP0 bits cannot be changed

Protected against Page

Program and Erase

(SE, BE)

Ready to accept Page

Program and Sector

Erase Instructions