S25FL002D0FMAI011 datasheet(20/38 Pages) SPANSION

20 / 38 page

S25FL Family (Serial Peripheral Interface)

30167A+1 June 9, 2004

P r el i m i n a r y

I n fo r m a t i o n

Figure 11. Page Program (PP) Instruction Sequence

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector.

Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been de-

coded, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low,

followed by the instruction code, and three address bytes on Serial Data Input

(SI). Any address inside the Sector (see Table 1 and Table 2) is a valid address

for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for

the entire duration of the sequence.

The instruction sequence is shown in Figure 12.

Chip Select (CS#) must be driven High after the eighth bit of the last address byte

has been latched in, otherwise the Sector Erase (SE) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle

(whose duration is tSE) is initiated. While the Sector Erase cycle is in progress,

the Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle,

and is 0 when it is completed. At some unspecified time before the cycle is com-

pleted, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to any memory area that is protected by

the Block Protect (BP1, BP0) bits (see Table 1 and Table 2) is not executed.

35 36 37 38 39

47 48 49 50 51 52 53 54 55

23 22 21

Data Byte 1

24-Bit Address

Instruction

Data Byte 2

Data Byte 3

Data Byte 256

MSB

SCK

432

CS#

S25FL002D0FMAI011 Datasheet(PDF) 20 Page - SPANSION