S25FL002D0FMAI011 datasheet(19/38 Pages) SPANSION

19 / 38 page

June 9, 2004 30167A+1

S25FL Family (Serial Peripheral Interface)

Pre limin ary

I n f o r m a t ion

(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress,

is rejected without having any effects on the cycle that is in progress.

Figure 10. Fast Read (FAST_READ) Instruction Sequence

Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN)

instruction must previously have been executed. After the Write Enable (WREN)

instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low,

followed by the instruction code, three address bytes and at least one data byte

on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 11.

If more than 256 bytes are sent to the device, the addressing will wrap to the

beginning of the same page, previously latched data are discarded and the last

256 data bytes are guaranteed to be programmed correctly within the same

page. If fewer than 256 Data bytes are sent to device, they are correctly pro-

grammed at the requested addresses without having any effects on the other

bytes of the same page.

Chip Select (CS#) must be driven High after the eighth bit of the last data byte

has been latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle

(whose duration is tPP) is initiated. While the Page Program cycle is in progress,

the Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,

and is 0 when it is completed. At some unspecified time before the cycle is com-

pleted, the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) instruction applied to a page that is protected by the Block

Protect (BP1, BP0) bits (see Table 1 and Table 2) is not executed.

CS#

SCK

Instruction

24-Bit

Address

Dummy Byte

High Impedance

DATA OUT 1

DATA OUT 2

MSB

28 29 30

31 32 33

34 35 36 37 38

40 41

42 43 44 45

23 22 21

S25FL002D0FMAI011 Datasheet(PDF) 19 Page - SPANSION

S25FL002D0FMAI011 Datasheet(HTML) 19 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL