S25FL002D0FMAI011 datasheet(21/38 Pages) SPANSION

21 / 38 page

June 9, 2004 30167A+1

S25FL Family (Serial Peripheral Interface)

Pre limin ary

I n f o r m a t ion

Figure 12. Sector Erase (SE) Instruction Sequence

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory.

Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been de-

coded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, fol-

lowed by the instruction code, on Serial Data Input (SI). No address is required

for the Bulk Erase (BE) instruction. Chip Select (CS#) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 13.

Chip Select (CS#) must be driven High after the eighth bit of the last address byte

has been latched in, otherwise the Bulk Erase (BE) instruction is not executed.

As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle

(whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the

Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle,

and is 0 when it is completed. At some unspecified time before the cycle is com-

pleted, the Write Enable Latch (WEL) bit is reset.

A Bulk Erase (BE) instruction is executed only if both the Block Protect (BP1, BP0)

bits (see Table 1 and Table 2) are set to 0. The Bulk Erase (BE) instruction is ig-

nored if one or more sectors are protected.

CS#

SCK

Instruction

24 Bit Address

28 29 30 31

23 22 21

MSB

S25FL002D0FMAI011 Datasheet(PDF) 21 Page - SPANSION