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MPF7100BVBA3ES Datasheet(PDF) 32 Page - NXP Semiconductors |
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MPF7100BVBA3ES Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 32 / 125 aaa-034299 Power Down Sequence Power Down Delay Regulator Outputs VSNVSx PWRON RESETBMCU OFF State Power Down Sequence Shutdown Event System On State Power Down Delay Figure 12. Power down delay During a Hard WD reset, the power down shall also wait until the power down delay is reached before it can start the new power up sequence. The default value of the OTP_PD_SEQ_DLY[1:0] bits on an unprogrammed OTP device is 00. 14.7 Fault detection Three types of faults are monitored per regulator: UV, OV, and ILIM. Faults are monitored during power up sequence, run, standby, and WD reset states. A fault event is notified to the MCU through the INTB pin if the corresponding fault is not masked. The fault configuration registers are reset to their default value after the power up sequence, and system must configure them as required during the boot-up process via I2C commands. For each type of fault, there is an I2C bit that is used to select whether the regulator is kept enabled or disabled when the corresponding regulator experiences a fault event. SWx_ILIM_STATE / LDOx_ILIM_STATE • 0 = regulator disable upon an ILIM fault event • 1 = regulator remains on upon an ILIM fault event SWx_OV_STATE / LDOx_OV_STATE • 0 = regulator disable upon an OV fault event • 1 = regulator remains On upon an OV fault event SWx_UV_STATE / LDOx_UV_STATE • 0 = regulator disable upon an UV fault event • 1 = regulator remains on upon an UV fault event The following table lists the functional bits associated with enabling/disabling the external regulators when they experience a fault. |
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