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MPF7100BVBA3ES Datasheet(PDF) 97 Page - NXP Semiconductors |
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MPF7100BVBA3ES Datasheet(HTML) 97 Page - NXP Semiconductors |
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97 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 97 / 125 AD DR Register Name R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 5D SW3 CONFIG1 R/W SW3_UV_ BYPASS SW3_OV_BYPASS SW3_ILIM_BYPASS SW3_UV_STATE SW3_OV_STATE SW3_ILIM_STATE SW3_WDBYPASS SW3_PG_EN 5E SW3 CONFIG2 R/W SW3_FLT_REN SW3DVS_RAMP[1:0] SW3ILIM[1:0] SW3PHASE[2:0] 5F SW3 PWRUP R/W SW3_SEQ[7:0] 60 SW3 MODE1 R/W — SW3_VTTEN SW3_PDGRP[1:0] SW3_STBY_MODE[1:0] SW3_RUN_MODE[1:0] 61 SW3 RUN VOLT R/W VSW3_RUN[7:0] 62 SW3 STBY VOLT R/W VSW3_STBY[7:0] 65 SW4 CONFIG1 R/W SW4_UV_ BYPASS SW4_OV_BYPASS SW4_ILIM_BYPASS SW4_UV_STATE SW4_OV_STATE SW4_ILIM_STATE SW4_WDBYPASS SW4_PG_EN 66 SW4 CONFIG2 R/W SW4_FLT_REN SW4DVS_RAMP[1:0] SW4ILIM[1:0] SW4PHASE[2:0] 67 SW4 PWRUP R/W SW4_SEQ[7:0] 68 SW4 MODE1 R/W — — SW4_PDGRP[1:0] SW4_STBY_MODE[1:0] SW4_RUN_MODE[1:0] 69 SW4 RUN VOLT R/W VSW4_RUN[7:0] 6A SW4 STBY VOLT R/W VSW4_STBY[7:0] 7D SW5CONFIG1 R/W SW5_UV_ BYPASS SW5_OV_BYPASS SW5_ILIM_BYPASS SW5_UV_STATE SW5_OV_STATE SW5_ILIM_STATE SW5_WDBYPASS SW5_PG_EN 7E SW5 CONFIG2 R/W SW5_FLT_REN — — SW5ILIM[1:0] SW5PHASE[2:0] 7F SW5 PWRUP R/W SW5_SEQ[7:0] 80 SW5 MODE1 R/W — — SW5_PDGRP[1:0] SW5_STBY_MODE[1:0] SW5_RUN_MODE[1:0] 81 SW5 RUN VOLT R/W — — — VSW5_RUN[4:0] 85 LDO1 CONFIG1 R/W LDO1_UV_ BYPASS LDO1_OV_BYPASS LDO1_ILIM_ BYPASS LDO1_UV_STATE LDO1_OV_STATE LDO1_ILIM_STATE LDO1_WDBYPASS LDO1_PG_EN 86 LDO1 CONFIG2 R/W LDO1_FLT_ REN LDO1_PDGRP[1:0] — — — LDO1_RUN_EN LDO1_STBY_EN 87 LDO1 PWRUP R/W LDO1_SEQ[7:0] 88 LDO1 RUN VOLT R/W — — — — VLDO1_RUN[3:0] 89 LDO1 STBY VOLT R/W — — — — VLDO1_STBY[3:0] 8B LDO2 CONFIG1 R/W LDO2_UV_ BYPASS LDO2_OV_BYPASS LDO2_ILIM_ BYPASS LDO2_UV_STATE LDO2_OV_STATE LDO2_ILIM_STATE LDO2_WDBYPASS LDO2_PG_EN 8C LDO2 CONFIG2 R/W LDO2_FLT_ REN LDO2_PDGRP[1:0] LDO2HW_EN VSELECT_EN — LDO2_RUN_EN LDO2_STBY_EN 8D LDO2 PWRUP R/W LDO2_SEQ[7:0] 8E LDO2 RUN VOLT R/W — — — — VLDO2_RUN[3:0] 8F LDO2 STBY VOLT R/W — — — — VLDO2_STBY[3:0] 9D VSNVS CONFIG1 R/W — — — — VSNVS2VOLT [1:0] VSNVS1VOLT [1:0] 9F PAGE SELECT R/TW — — — — — PAGE[2:0] 16.2 PF7100 ASIL B OTP mirror register map (page 1) Reset types OFF_OTP Register loads the OTP mirror register values during power up OTP Register available in OTP bank only, reset from fuses when VIN crosses UVDET threshold VSNVS Reset when BOS has no valid input. VIN < UVDET ADDR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 A0 OTP FSOB SELECT — — — OTP_FSOB_ ASS_EN OTP_FSOB_ SOFTFAULT OTP_FSOB_ WDI OTP_FSOB_ WDC OTP_FSOB_ HARDFAULT A1 OTP I2C — — — OTP_I2C_ SECURE_EN OTP_I2C_ CRC_EN OTP_I2C_ADD[2:0] A2 OTP CTRL1 — — OTP_EWARN_TIME[1:0] OTP_FS_BYPASS OTP_STANDBYINV OTP_PG_ACTIVE OTP_PG_CHECK |
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