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MPF7100BVBA3ES Datasheet(PDF) 91 Page - NXP Semiconductors |
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MPF7100BVBA3ES Datasheet(HTML) 91 Page - NXP Semiconductors |
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91 / 125 page ![]() NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 91 / 125 • When WD_STBY_EN = 0, the internal watchdog timer operation during standby is disabled. • When WD_STBY_EN = 1, the internal watchdog timer operation during standby is enabled. The OTP_WD_STBY_EN bit selects whether the watchdog is active in standby mode by default or not. 15.10.2 Watchdog reset behaviors When a watchdog event is started, a watchdog (WD) reset is performed. There are two types of watchdog reset: • Soft WD reset • Hard WD reset A soft WD reset is used as a safe way for the MCU to force the PMIC to return to a known default configuration without forcing a POR Reset on the MCU. During a Soft WD reset, the RESETBMCU remains deasserted all the time. Upon a soft WD reset, a partial OTP register reload is performed on the registers as shown in Table 74. Table 74. Soft WD register reset Bit name Register Bits Configuration registers STANDBYINV CTRL2 2 RUN_PG_GPO CTRL2 1 STBY_PG_GPO CRTL2 0 RESETBMCU_SEQ[7:0] RESETBMCU PWRUP 7:0 PGOOD_SEQ[7:0] PGOOD PWRUP 7:0 WD_EN CTRL1 3 WD_DURATION[3:0] WD CONFIG 3:0 WD_STBY_EN CTRL1 2 WDI_STBY_ACTIVE CTRL1 1 SW registers SWx_WDBYPASS SWx CONFIG1 1 SWx_PG_EN SWx CONFIG1 0 SWxDVS_RAMP SWx CONFIG2 6:5 SWxILIM[1:0] SWx CONFIG2 4:3 SWxPHASE[2:0] SWx CONFIG2 2:0 SWx_SEQ[7:0] SWx PWRUP 7:0 SWx_PDGRP[1:0] SWx MODE 5:4 SWx_STBY_MODE [1:0] SWx MODE 3:2 SWx RUN_MODE [1:0] SWx MODE 1:0 VSWx_RUN [7:0] SWx RUN VOLT 7:0 VSWx_STBY [7:0] SWx STBY VOLT 7:0 VSW5 [4:0] SW5 VOLT 4:0 SW3_VTTEN SW3_CONFIG2 6 |
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