NXP Semiconductors

SL3S1205_15

UCODE 8/8m

Bank

Address

Type

Content

Initial

Remark

00h to 1Fh

reserved

Kill password

all 00h

unlocked memory

Bank 00

20h to 3Fh

reserved

Access password

all 00h

unlocked memory

00h to 0Fh

EPC

CRC-16: refer to "EPC

Global Gen2v2"

memory mapped

calculated CRC

10h to 14h

EPC

EPC length

00110b

unlocked memory

15h

EPC

UMI

1b

hardwired to 1

16h

EPC

XPC indicator

0b

hardwired to 0

17h to 1Fh

EPC

numbering system indicator 00h

unlocked memory

Bank 01

EPC

20h to 7Fh

EPC

EPC

[1]

unlocked memory

200h

EPC

EPC check

0b

indicator bit

201h

EPC

EPC correction

0b

indicator bit

202h

EPC

EPC NOK

0b

indicator bit

203h

EPC

EPC+TID

0b

action bit[2]

204h

EPC

Brand Identifier

0b

action bit[2]

205h

EPC

Self Adjust Cap 1

0b

indicator bit

206h

EPC

Self Adjust Cap 0

0b

indicator bit

207h

EPC

Self Adjust disable

0b

permanent bit[3]

208h

EPC

RFU

0b

locked memory

209h

EPC

max. backscatter strength

1b

permanent bit[3]

20Ah

EPC

RFU

0b

locked memory

20Bh

EPC

RFU

0b

locked memory

20Ch

EPC

User Memory check

0b

indicator bit

20Dh

EPC

User Memory correction

0b

indicator bit

20Eh

EPC

User Memory NOK

0b

indicator bit

Bank 01

Config Word

20Fh

EPC

PSF flag

0b

permanent bit[3]

00h to 07h

TID

allocation class identifier

1110 0010b

locked memory

08h to 13h

TID

tag mask designer identifier 1000 0000 0110b

locked memory

14h

TID

config word indicator

1b[4]

locked memory

15h to 1Fh

TID

tag model number

TMNR[5]

locked memory

20h to 2Fh

TID

XTID header

2000h

locked memory

Bank 10

TID

30h to 5Fh

TID

serial number

SNR

locked memory

Bank 11

User Memory

00h to 1Fh

UM

User Memory

all 00h

unlocked memory

Table 9. UCODE 8m overall memory map

[1]

HEX E280 6994 0000 nnnn nnnn nnnn where n are the nibbles of the SNR from the TID

[2]

Action bits: meant to trigger a feature upon a SELECT command on the related bit ref feature control mechanism, see Section 9.6.1

[3]

Permanent bit: permanently stored bits in the memory; Read/Writeable according to EPC bank lock status, see Section 9.6.1

[4]

Indicates the existence of a Configuration Word at the end of the EPC number

[5]

See Figure 6

SL3S1205_15

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 3.5 — 1 April 2021

COMPANY PUBLIC

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