SL3S1205FUD2SLASHHAP datasheet(12/38 Pages) NXP

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NXP Semiconductors

SL3S1205_15

UCODE 8/8m

Pad shear strength

> 70 MPa

Pad height

3 μm

Pad height uniformity

– within a die

max. 2 μm

– within a wafer

max. 4 μm

Pad flatness

max. 3 μm

Pad size

– RF1, RF2 (max. details see wafer layout)

151.5 μm × 278 μm

– TP1, TP2 (max. details see wafer layout)

134.2 μm × 100 μm

Pad size variation

± 5 μm

Table 3. 8 inch specification with Large Pads, stealth dicing...continued

8.1.2 12 inch Wafer with Large Pads

See "Data sheet - Delivery type description – General specification for 12" wafer on UV-

tape with electronic fail die marking, BU-S&C document number: 1862**"

Wafer

Designation

each wafer is scribed with batch number and

wafer number

Diameter

300 mm (12") unsawn

Thickness

120 μm ± 15 μm

Number of pads

Pad location

non-diagonal / placed in chip corners

Process

CMOS 0.14 μm

Batch size

25 wafers

Net printed dies per wafer

258934

Wafer backside

Material

Treatment

ground and stress release

Roughness

Ra max. 0.5 μm, Rt max. 5 μm

Chip dimensions

Die size excluding scribe

0.465 mm × 0.475 mm = 0.22 mm2

Scribe line width:

x-dimension = 35 μm

y-dimension = 35 μm

Passivation on front

Type

Sandwich structure

Material

PE-Nitride (on top)

Thickness

1.75 μm total thickness of passivation

Polyimide spacer

10 μm ± 2 μm

Table 4. 12 inch specification with Large Pads, conventional dicing

SL3S1205_15

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 1 April 2021

COMPANY PUBLIC

398435

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