SL3S1205FUD2SLASHHAP datasheet(37/38 Pages) NXP

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NXP Semiconductors

SL3S1205_15

UCODE 8/8m

Figures

Fig. 1.

Block diagram of UCODE 8/8m IC ....................6

Fig. 2.

Pinning bare die, Large Pads ............................7

Fig. 3.

UCODE 8/8m, 8" wafer layout, Large Pads,

stealth dicing ..................................................... 8

Fig. 4.

UCODE 8/8m, 12" wafer layout, Large

Pads, conventional dicing ................................. 9

Fig. 5.

UCODE 8/8m, 12" wafer layout, Large

Pads, plasma dicing ........................................10

Fig. 6.

UCODE 8/8m TID memory structure ...............19

Fig. 7.

Pre-serialization of 96-bit EPC ........................ 24

Fig. 8.

Standard antenna design versus single-slit

antenna ............................................................25

Fig. 9.

Single-slit assembly .........................................25

Fig. 10.

Rotation tolerant pad design ........................... 26

Fig. 11.

Dual axis glue spacer ..................................... 26

SL3S1205_15

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 1 April 2021

COMPANY PUBLIC

398435

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SL3S1205FUD2/HAP Datasheet(PDF) 37 Page - NXP Semiconductors