SL3S1205FUD2SLASHHAP datasheet(11/38 Pages) NXP

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NXP Semiconductors

SL3S1205_15

UCODE 8/8m

8 Mechanical specification

The UCODE 8 wafers are available in 120 μm thickness. For Large Gold Pads the 120

μm thick wafer is enhanced with 10 μm Polyimide spacer resulting in less coupling

between the antenna and the active circuit, leaving a larger process window for

assembly.

8.1 Wafer specification

8.1.1 8 inch Wafer with Large Pads, stealth dicing

See "Data sheet - Delivery type description – General specification for 8" wafer on UV-

tape with electronic fail die marking, BU-S&C document number: 1093**"

Wafer

Designation

each wafer is scribed with batch number and

wafer number

Diameter

200 mm (8") unsawn- 205 mm typical sawn

on foil

Thickness

120 μm ± 15 μm

Number of pads

Pad location

non-diagonal / placed in chip corners

Process

CMOS 0.14 μm

Batch size

25 wafers

Net printed dies per wafer

120794

Wafer backside

Material

Treatment

ground and stress release

Roughness

Ra max. 0.5 μm, Rt max. 5 μm

Chip dimensions

Die size excluding scribe

0.465 mm × 0.475 mm = 0.22 mm2

Scribe line width:

x-dimension = 15 μm

y-dimension = 15 μm

Passivation on front

Type

Sandwich structure

Material

PE-Nitride (on top)

Thickness

1.75 μm total thickness of passivation

Polyimide spacer

10 μm ± 2 μm

Au pads

Pad material

> 99.9 % pure Au

Pad hardness

35 – 80 HV 0.005

Table 3. 8 inch specification with Large Pads, stealth dicing

SL3S1205_15

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.5 — 1 April 2021

COMPANY PUBLIC

398435

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