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SH79F6488P/080PR Datasheet(PDF) 121 Page - SINOWEALTH Electronic Ltd

Part # SH79F6488P/080PR
Description  Enhanced 8051 Microcontroller with 20bit Σ-ΔADC and LCD Driver
PDF  152 Pages
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Manufacturer  SINOWEALTH [SINOWEALTH Electronic Ltd]
Direct Link  https://en.sinowealth.com
Logo SINOWEALTH - SINOWEALTH Electronic Ltd

SH79F6488P/080PR Datasheet(HTML) 121 Page - SINOWEALTH Electronic Ltd

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SH79F6488/SH79F6489
121
Table 8.41 Endpoint 2 Control Register
D8H (Bank1)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EP2CON
IEP2DTG
OEP2DTG
-
-
IEP2STL
IEP2RDY
OEP2STL OEP2RDY
R/W
R/W
R/W
-
-
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
0
0
-
-
0
0
0
0
Bus Reset Value
(USB RESET)
0
0
-
-
0
U
0
U
USB Software Reset
Value
0
0
-
-
0
0
0
0
Bit No.
Bit Mnemonic
Description
7
IEP2DTG
Endpoint 2 IN Data Toggle bit
0: Reading out ‘0’ indicates that the next data toggle bit is Data1, writing in ‘0’
indicates that the next data toggle bit will be setted as Data1
1: Reading out ‘1’ indicates that the next data toggle bit is Data0, writing in ‘1’
indicates that the next data toggle bit will be setted as Data0
6
OEP2DTG
Endpoint 2 OUT Data Toggle bit
0: Reading out ‘0’ indicates that the next data toggle bit is Data1, writing in ‘0’
indicates that the next data toggle bit will be setted as Data1
1: Reading out ‘1’ indicates that the next data toggle bit is Data0, writing in ‘1’
indicates that the next data toggle bit will be setted as Data0
3
IEP2STL
Endpoint 2 IN STALL Enable bit
0: Disable Endpoint 2 IN STALL
1: Enable Endpoint 2 IN STALL, When the host sends IN transaction to Endpoint
2, returns a STALL
2
IEP2RDY
Endpoint 2 IN State bit
0: Endpoint 2 IN is not ready, When the host sends IN transaction to Endpoint 2,
returns a NAK
1: Endpoint 2 IN is ready
When the host sends IN transaction to Endpoint 2, if this bit is ‘1’, the USB
transceiver sends data in Endpoint 2 buffer, and after receiving an ACK from the
host, this bit is cleared, generate Endpoint 2 IN interrupt.
Writing the data(need to be sent to the host) into Endpoint 2 buffer again by
software, and setting this bit indicates the next IN transaction can be received.
Software write 0 has no effect.
1
OEP2STL
Endpoint 2 OUT STALL Enable bit
0: Disable Endpoint 2 OUT STALL
1: Enable Endpoint 2 OUT STALL, When the host sends OUT transaction to
Endpoint 2, returns a STALL
0
OEP2RDY
Endpoint 2 OUT State bit
0: Endpoint 2 OUT is not ready, When the host sends OUT transaction to
Endpoint 2, returns a NAK
1: Endpoint 2 OUT is ready
When the host sends OUT transaction to Endpoint 2, if this bit is ‘1’, the USB
transceiver writes data into Endpoint 2 buffer, and after returning an ACK to the
host, this bit is cleared, generate Endpoint 2 OUT interrupt.
After reading out the data in Endpoint 2 buffer by software, setting this bit
indicates the next OUT transaction can be received. Software write 0 has no
effect.



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