AMD-K6-2ESLASH233AMZ datasheet(129/332 Pages) AMD

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Chapter 5

Signal Descriptions

111

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

5.32

KEN# (Cache Enable)

Pin Attribute

Input

Pin Location

W-05

Summary

If KEN # is sampled asserted, it indicates that the address

presented by the processor is cacheable. If KEN # is sampled

asserted and the processor intends to perform a cache-line fill

(signified by the assertion of CACHE#), the processor executes

a 32-byte burst read cycle and expects to sample BRDY #

asserted a total of four times. If KEN # is sampled negated

during a read cycle, a single-transfer cycle is executed and the

processor does not cache the data. For write cycles, CACHE# is

asserted to indicate the current bus cycle is a modified

cache-line writeback. KEN# is ignored during writebacks.

If PCD is asserted during a bus cycle, the processor does not

cache any data read during that cycle, regardless of the state of

KEN #. See “PCD (Page Cache Disable)” on page 115 for more

details.

If the processor has sampled the state of KEN# during a cycle,

and that cycle is aborted due to the sampling of BOFF #

asserted, the system logic must ensure that KEN# is sampled in

the same state when the processor restarts the aborted cycle.

Sampled

KEN# is sampled on the clock edge on which the first BRDY# or

NA # of a read cycle is sampled asserted. If the read cycle is a

burst, KEN # is ignored during the last three assertions of

BRDY #. KEN # is sampled during read cycles only when

CACHE# is asserted.

AMD-K6-2E/233AMZ Datasheet(PDF) 129 Page - Advanced Micro Devices