AX88180 datasheet(12/47 Pages) ASIX

12 / 47 page

AX88180

ASIX ELECTRONICS CORPORATION

3.0 Functional Description

3.1 Host Interface

AX88180 supports a very simple SRAM-like interface. There are only 3 control signals to operate the read or write.

For write operation, host activates CSN and WEN to low with address and data bus. AX88180 will decode and latched the

data into internal buffer. For normal operation, the WEN needs at least 4 clocks duration for one 32/16-bit write operation.

The CSN can always be driven, but WEN must at least be de-asserted 1 clock before next access. For read operation, host

asserts CSN and OEN at least 5 clocks to AX88180, the data will be valid after 4 clocks. AX88180 also support burst mode

if host reads/writes AX88180 by continuous access. Note: The burst mode only supports in TX/RX, not supports in

registers read/write. That is, reads RX area from XXXX_0000 to XXXX_7FFF or writes TX area from XXXX_8000 to

XXXX_FBFF can be accessed by burst mechanism.

3.2 System Address Range

AX88180 is suitable to attach to SRAM controller, so it needs 64K memory space for operation. The designer can

allocate any block (64K) in system space. From offset 0x0000 to 0x7FFF is for RX operation, and offset 0x8000 to

0xFBFF is for TX operation. The internal configuration register of AX88180 is allocated in offset 0xFC00 to 0xFCFF.

Below is the mapping of addressing.

Figure 3: 32-bit mode address mapping

3.3 TX Buffer Operation

AX88180 employs 4 descriptors to maintain transmit information, such as packet length, start bit. These descriptors

are located in offset 0xFC20, 0xFC24, 0xFC28 and 0xFC2C. Driver can choose any descriptor whenever there is data

needed to be transmitted. Since there are only 4 descriptors, upon running out of descriptors, driver must wait for the

descriptor is to be released by AX88180.

3.4 RX Buffer Operation

AX88180 is built a 32K SRAM for RX operation. It utilizes ring structure to maintain the input data from PHY and

read out to host.

There are two pointer registers located in offset 0xFC34 and oxFC38. AX88180 will maintain RXCURT

data from AX88180 and maintains the RXBOUND register. When driver finishes reading packet, it must update

RXBOUND according to the packet length. AX88180 utilizes RXCURT and RXBOUND to provide receive buffer status,

full or empty.

R X

ar ea

3276 8 b y t e s

XXXX _ 0000h

XXXX _8000 h

XXXX_ F C 0 0 h

T X

ar ea

3174 4 b y t e s

R e g i s t er s ar ea

2 56 b y t e s

XXXX_ F D0 0 h

N o u s e d ar ea

7 68 b y t e s

XXXX_ F F F F h

AX88180 Datasheet(PDF) 12 Page - ASIX Electronics Corporation

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