AX88180 datasheet(8/47 Pages) ASIX

8 / 47 page

AX88180

ASIX ELECTRONICS CORPORATION

2.0 Signal Description

2.1 Signal Type Definition

I3:

Input, 3.3V with 5V tolerance

I2:

Input, 2.5V with 3.3V tolerance

I25

Input 2.5V only

O3:

Output, 3.3V

O2:

Output, 2.5V

IO3:

Input/Output, input 3.3V with 5V tolerance

IO2:

Input/Output, input 2.5V with 3.3V tolerance

TSO:

Tri-State Output

OD:

Open Drain allows multiple devices to share as a wire-OR

PD:

Internal 75K Pull Down

PU:

Internal 75K Pull Up

GND:

Digital Ground

VCC3:

3.3V power

VCC2:

2.5V power

Input only

Output only

IO:

Input/Output

2.2 RGMII/MII Interface

Table 1 : RGMII/MII Interface signals group

Pin Name Type

Pin NO

Pin Description

CLK125

Free running clock 125MHz from OSC or Giga-PHY.

TXEN

O2, 12mA 66

Transmit Enable:

TXEN is transition synchronously with respect to the rising and falling edge of

TXCX. TXEN indicates that the port is presenting nibbles on TXD [3:0] for

transmission.

TXD[3:0]

O2, 12mA 61,62,63,65

Transmit Data:

TXD[3:0] is transition synchronously with respect to the rising and falling edge of

TXCX.

In rising edge TXD[3:0] is as general TD[3:0] and falling edge TXD[3:0]

is as TD[7:4]. TD[7:0] is used in AX88180 as byte unit.

TXCX

O2, 12mA 68

125MHz Clock Output:

It is a continuous 125 MHz clock Output to Giga-PHY operating in RGMII mode. It

is a timing reference for TXEN and TXD[3:0]. For normal operation, this pin will

be connected to Giga-PHY.

GTXCLK O2, 12mA 67

125MHz Clock Output:

It is a continuous 125 MHz clock output. This pin is for internal debug purpose only

and should be floating for normal operation.

RXCLK

Receive Clock:

RXCLK is a continuous clock that provides the timing reference for RXDV,

RXD[3:0]. This clock is provided from PHY.

RXD[3:0] I2

77,76,75,74 Receive Data:

RXD[3:0] is driven by the PHY synchronously with respect to RXCLK. In rising

edge RXD[3:0] is as RD[3:0] and falling edge is as RD[7:4]. RD[7:0] is used in

AX88180 as byte unit.

RXDV

Receive Data Valid:

RXDV is driven by the PHY synchronously with respect to RXCLK in rising and

falling edge. It is asserted high when valid data is present on RXD [3:0].

COL

Collision:

This signal is driven by PHY when collision is detected.

CRS

Carrier Sense:

AX88180 Datasheet(PDF) 8 Page - ASIX Electronics Corporation

AX88180 Datasheet(HTML) 8 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL